Using CSP to Verify Aspects of an occam-to-FPGA Compiler
نویسندگان
چکیده
This paper reports on the progress made in developing techniques for the verification of an occam to FPGA compiler. The compiler converts occam 1 programs into logic circuits that are suitable for loading into field-programmable gate arrays (FPGAs). Several levels of abstraction of these circuits provide links to conventional hardware implementations. Communicating Sequential Processes (CSP) has then been used to model these circuits. This CSP has been subjected to tests for deadlock and livelock freedom using the Failures-Divergence Refinement tool (FDR). In addition, FDR has been used to prove that the circuits emitted have behaviours equivalent to CSP specifications of the original occam source codes.
منابع مشابه
Steps in the Verification of an Occam-to-FPGA Compiler
This paper reports on the progress made in developing techniques for the verification of an Occam to FPGA compiler. Communicating Sequential Processes (CSP) has been used to model the circuits generated by our compiler. This CSP has then been subjected to tests for deadlock and livelock freedom using the Failures-Divergence Refinement tool (FDR, [6]). In addition, FDR has been used to prove tha...
متن کاملAutomatically Generated CSP Provides Verification for occam-derived Logic Circuits
This paper reports on the creation of a new back-end for the authors’ occam-to-FPGA compiler. The creation of Communicating Sequential Processes (CSP) models of compiler-generated logic circuits has thus recently been automated. These models are now being used to provide reference testing of the compiler as it undergoes further implementation and refinement, as well as to verify components of p...
متن کاملA CSP Model for Mobile Channels
CSP processes have a static view of their environment – a fixed set of events through which they synchronise with each other. In contrast, the π-calculus is based on the dynamic construction of events (channels) and their distribution over pre-existing channels. In this way, process networks can be constructed dynamically with processes acquiring new connectivity. For the construction of comple...
متن کاملR16: A New Transputer Design for FPGAs
This paper describes the ongoing development of a new FPGA hosted Transputer using a Load Store RISC style Multi Threaded Architecture (MTA). The memory system throughput is emphasized as much as the processor throughput and uses the recently developed Micron 32MByte RLDRAM which can start fully random memory cycles every 3.3ns with 20ns latency when driven by an FPGA controller. The R16 shares...
متن کاملAn Automatic Translation of CSP to Handel-C
We present tools that convert a subset of CSP into Handel-C code. Handel-C was derived from the original occam concurrency language, but has a syntax similar to the standard C programming language. It compiles to produce files to program an FPGA. We thus now have a process that can directly generate hardware from a verified high-level description. The CSP to Handel-C translator makes use of the...
متن کامل